The present invention relates to a dynamic read only memory with a large capacity.
In the dynamic read only memory (referred to as a dynamic ROM) with large capacity, it is a common practice that the memory area is divided into n blocks for improving the frequency characteristics. An example of such a ROM is illustrated in FIG. 1. The timing charts for explaining the operation of the FIG. 1 ROM are shown in FIGS. 2A to 2F. The ROM of FIG. 1 is made up of two blocks, ROM block 1 and ROM block 2, and has a total memory capacity of 512 bits. In FIG. 1, numeral 1 designates an address decoder, 2 a column address decoder, 3 a precharge circuit, 4 a discharge circuit, and 5 a latch circuit for fetching data stored in ROM block 1 and ROM block 2 by a clock .phi..sub.L1 (FIG. 2C) and outputting the same by a clock .phi..sub.L2 (FIG. 2D). Reference numeral 6 represents a P channel MOSFET (metal oxide semiconductor field effect transistor), 7 an N channel MOSFET, V.sub.DD a power source potential, and V.sub.SS a reference potential, for example, ground potential.
As shown in FIGS. 2A to 2F, when the clock pulse .phi..sub.ROM (FIG. 2B) is "1" a time t.sub.0, all the N channel MOSFETs 7 in the discharge circuit 4 are ON. Further, the column lines in ROM block 1 and ROM block 2 are discharged and these output data are reset to "0". When at time t.sub.1 the clock pulse .phi..sub.ROM is "0", the N channel MOSFETs 7 are all OFF, while the P channel MOSFETs 6 in the precharge circuit 3 are all ON. Then address inputs A.sub.5 and A.sub.6 designate one of four output lines for each of output data Dj (J=0-3) and address inputs Ai (i=0-4) designate one of the row lines so that a cell is selected. In response to data at the selected cell, the output line of the selected cell is charged as shown by a solid line in FIG. 2E or kept at a discharge state as shown by a broken line in FIG. 2E. When the clock .phi..sub.L1 is "1" the output data Dj on the output line of the selected cell is latched in the latch circuit 5. Then, when the clock .phi..sub.L2 is "1", the data Dj stored in the latch circuit 5 is output as output data (FIG. 2F). In ROM block 1 and ROM block 2, output data Dj or Dj' (j=0-3) from the non-selected block (i.e. the memory block which does not include a selected cell) are all "1". For example, when ROM block 1 is selected, output data D.sub.0 ' to D.sub.3 ' of the non-selected ROM block 2 are all "1". This fact indicates that for every reading operation, the charge or discharge current flows through the output lines of the output data Dj' (j=0-3) of the non-selected ROM block, thereby wasting electric power.